A 4.9-GHz low power, low jitter, LC phase locked loop

@article{Liu2010A4L,
  title={A 4.9-GHz low power, low jitter, LC phase locked loop},
  author={Tiankuan Liu},
  journal={Journal of Instrumentation},
  year={2010},
  volume={5}
}
  • Tiankuan Liu
  • Published 2010
  • Physics
  • Journal of Instrumentation
  • This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-μm Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has been investigated and traced to the first stage of the divider chain. The power consumption at the… CONTINUE READING

    Figures from this paper.

    References

    Publications referenced by this paper.
    SHOWING 1-3 OF 3 REFERENCES
    A 16:1 serializer ASIC for data transmission at 5 Gbps
    16
    Development of new readout electronics for the ATLAS LAr Calorimeter at the sLHC
    9
    The Design of a High Speed Low Power Phase Locked Loop, presented at the topical workshop on electronics in particle physics (TWEPP)
    • 2009