A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS

@article{Pellerano2009A4F,
  title={A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS},
  author={Stefano Pellerano and Paolo Madoglio and Yorgos Palaskas},
  journal={2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers},
  year={2009},
  pages={226-227,227a}
}
Local-oscillator (LO) pulling is a typical issue in fully integrated transceivers. To offset the oscillator frequency from the PA output frequency, SSB mixing or division-by-2 is typically used [1]. However, the first might require additional filtering to remove mixing spurs and the latter is still sensitive to second-harmonic pulling. The divider described in this paper prevents LO pulling by introducing a fractional ratio between input and output frequencies. Since fractional spurs are… CONTINUE READING