A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

@article{Satpathy2017A4D,
  title={A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS},
  author={Sudhir Satpathy and Sanu K. Mathew and Vikram Suresh and Mark Anders and Himanshu Kaul and Amit Agarwal and Steven Hsu and Gregory K. Chen and Ram Krishnamurthy and Vivek De},
  journal={IEEE Journal of Solid-State Circuits},
  year={2017},
  volume={52},
  pages={940-949}
}
This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark… CONTINUE READING

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