A 4 by 28.3 Gb/s SFI-S SerDes in 130 nm SiGe

@article{Krawczyk2010A4B,
  title={A 4 by 28.3 Gb/s SFI-S SerDes in 130 nm SiGe},
  author={Thomas W. Krawczyk and Todd Cooper and Samuel Steidl and Peter F. Curran and Masashi Yamagata and Song Shang and Tony Liu and James Pulver and Cliff Duong and Zuoding Wang and Darren Walworth and Craig Hornbuckle and David Grant Rowe},
  journal={2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)},
  year={2010},
  pages={1-4}
}
A 4 by 28.3 to 10 by 11.32 Gb/s SFI-S compliant two chip SerDes for 100 Gb/s applications was fabricated using IBM's SiGe 130 nm 8HP process (210 GHz fT). The Multiplexer receives 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s, and outputs four lanes at 28.3 Gb/s, with a maximum output of 1.2 Vpp differential. The Demultiplexer receives four channels at 28.3 Gb/s, recovers clock and data with a sensitivity of 40 mV, and outputs 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s. 

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A 39.8 Gb/s to 43.1 Gb/s SFI-5 Compliant 16:1 Multiplexer and 1:16 Demultiplexer for Optical Communication Systems

T. Krawczyk
IEEE Custom Integrated Circuits Conference, • 2003
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