A 4-bit CMOS full adder of 1-bit hybrid 13T adder with a new SUM circuit

@article{Lee2016A4C,
  title={A 4-bit CMOS full adder of 1-bit hybrid 13T adder with a new SUM circuit},
  author={Shing Jie Lee and Siti Hawa Binti Ruslan},
  journal={2016 IEEE Student Conference on Research and Development (SCOReD)},
  year={2016},
  pages={1-5}
}
Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 4-bit FA using complementary metal oxide semiconductor (CMOS) technology had been designed successfully. A 1-bit hybrid FA (HFA) using 13 transistors (13T) with a new SUM circuit is the basis for the building block of the 4-bits FA. Four HFAs are cascaded together and… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-2 OF 2 CITATIONS

Similar Papers

Loading similar papers…