A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme


We propose an MRAM macro architecture for SoCs to reduce their area size. The .shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology', which enables the same fast access time as and with smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-mum CMOS process and a 0… (More)

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