A 4-GS/s 4-bit Flash ADC in 0.18- $\mu{\hbox {m}}$ CMOS

@article{Park2007A44,
  title={A 4-GS/s 4-bit Flash ADC in 0.18- \$\mu\{\hbox \{m\}\}\$ CMOS},
  author={Sunghyun Park and Yorgos Palaskas and M. P. Flynn},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={1865-1872}
}
A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The… CONTINUE READING
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