A 4-GS/s 4-bit Flash ADC in 0.18- $\mu{\hbox {m}}$ CMOS

  title={A 4-GS/s 4-bit Flash ADC in 0.18- \$\mu\{\hbox \{m\}\}\$ CMOS},
  author={Sunghyun Park and Yorgos Palaskas and M. P. Flynn},
  journal={IEEE Journal of Solid-State Circuits},
A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 28 references

The Design of CMOS Radio-Frequency Integrated Circuits

T. Lee
View 4 Excerpts
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View 5 Excerpts
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Principles of CMOS VLSI Design

N.H.E. Weste, K. Eshraghian
View 5 Excerpts
Highly Influenced

A regenerative comparator structure with integrated inductors

IEEE Transactions on Circuits and Systems I: Regular Papers • 2006
View 3 Excerpts
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A 4GS/s 4b Flash ADC in 0.18/spl mu/m CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers • 2006
View 1 Excerpt

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers • 2006
View 1 Excerpt

A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005. • 2005
View 1 Excerpt

Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005. • 2005
View 2 Excerpts

A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) • 2004

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K. Uyttenhove, M.S.J. Steyaert
IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1115–1122, Jul. 2003. • 2003