A 4 . 9-GHz Low Power , Low Jitter , LC Phase Locked Loop

@inproceedings{Liu2010A4,
  title={A 4 . 9-GHz Low Power , Low Jitter , LC Phase Locked Loop},
  author={Tiankuan Liu},
  year={2010}
}
This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-μm Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has been investigated and traced to the first stage of the divider chain. The power consumption at the… CONTINUE READING
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Development of New Readout Electronics for the ATLAS LAr Calorimeter at the sLHC, presented at the topical workshop on electronics in particle physics (TWEPP)

  • Arno Straessner
  • 2009
1 Excerpt

The Design of a High Speed Low Power Phase Locked Loop, presented at the topical workshop on electronics in particle physics (TWEPP)

  • Tiankuan Liu
  • 2009
1 Excerpt

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