A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s

Abstract

In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to–floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm.

DOI: 10.1109/ISSCC.2010.5433949
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@inproceedings{Marotta2010A33, title={A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s}, author={G. G. Marotta and Agostino Macerola and A. D'Alessandro and A. Torsi and C. Cerafogli and C. Lattaro and C. Musilli and D. Rivers and Emanuele Sirizotti and F. Paolini and G. Imondi and G. Naso and Giovanni Santin and L. Botticchio and Luca De Santis and Luigi Pilolli and M. L. Gallese and Michele Incarnati and M. Tiburzi and P. Conenna and S. Perugini and Violante Moschiano and W. Di Francesco and Matt Goldman and Chris Haid and D. Di Cicco and D. Orlandi and F. Rori and Massimo Rossini and Tommaso Vali and Ramin Ghodsi and Frank Roohparvar}, booktitle={ISSCC}, year={2010} }