• Corpus ID: 15737701

A 3GHz Low-offset Fully Dynamic Latched Comparator for High-Speed and Low-Power ADCs

@inproceedings{Vali2013A3L,
  title={A 3GHz Low-offset Fully Dynamic Latched Comparator for High-Speed and Low-Power ADCs},
  author={Shaik Mastan Vali and P. Rajesh},
  year={2013}
}
In this paper, performances of various types of dynamic latched comparators are compared in terms of their offset voltages, speed and power. The accuracy of comparators, which is defined by its offset, along with power consumption, speed is of keen interest in achieving overall higher performance of ADCs. This can be achieved by the fully dynamic latched comparator which is proposed in this paper. This comparator shows 14.6mV offset which is small when compared to other dynamic comparators and… 

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References

SHOWING 1-10 OF 12 REFERENCES

A low-noise self-calibrating dynamic comparator for high-speed ADCs

This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage

CMOS dynamic comparators for pipeline A/D converters

Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are

Yield and speed optimization of a latch-type voltage sense amplifier

A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level,

Kickback noise reduction techniques for CMOS latched comparators

TLDR
This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

TLDR
This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator and indicates that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts.

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range.

Low-power high-speed low-offset fully dynamic CMOS latched comparator

....................................................................................................................... 3 Acknowledgements

C.Vital, “Kickback Noise Reduction Techniques for CMOS Latched Comparator

  • IEEE Transactions on Circuits and Systems, vol.53,
  • 2006

Design of a CMOS Comparator for Low Power and High Speed

  • Internationl Journal of Electronic Engineering Research, vol. 2, no. 1, pp. 29-34, 2010
  • 2010