A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

@article{Kurita2007A3S,
  title={A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology},
  author={Yutaka Kurita and S. Matsui and Nobukazu Takahashi and Kei Soejima and M. Komuro and Masayasu Itou and Chika Kakegawa and Masaya Kawano and Yoshimi Egawa and Yuji Saeki and Hiroyuki Kikuchi and Osayoshi Kato and Azusa Yanagisawa and Takaharu Mitsuhashi and Masaaki Ishino and Kimio Shibata and Shiro Uchiyama and Jin-ichiro Yamada and Hidekazu Ikeda},
  journal={2007 Proceedings 57th Electronic Components and Technology Conference},
  year={2007},
  pages={821-829}
}
A general-purpose 3D-LSI platform technology for a high-capacity stacked memory integrated on a logic device was developed for high-performance, power-efficient, and scalable computing. SMAFTI technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was introduced for interconnecting the 3D stacked memory and the logic device. A DRAM-compatible manufacturing process was realized through the use of a "via-first" process and highly doped poly-Si… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-2 OF 2 REFERENCES

Inter-chip Connection Structure through an Interposer with High Density Via,

M. Takahashi, M. Tago, +5 authors T. Murakami
  • Proc. of 12th Symposium on "Microjoining and Assembly Technology in Electronics" (Mate
  • 2006
VIEW 2 EXCERPTS

Development of High-Density Inter-ChipConnection Structure Package,

Y. Kurita, K. Soejima, +6 authors M. Kawano
  • Proc. of 15th' Micro Electronics Symposium (MES
  • 2005
VIEW 1 EXCERPT