A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

@article{Kawano2006A3P,
  title={A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer},
  author={Masaya Kawano and Shiro Uchiyama and Yoshimi Egawa and Nobukazu Takahashi and Yutaka Kurita and Kei Soejima and Matahiro Komuro and S. Matsui and Kimio Shibata and Jin-ichiro Yamada and Masaaki Ishino and Hidekazu Ikeda and Yuji Saeki and O. Kato and Hiroyuki Kikuchi and Takaharu Mitsuhashi},
  journal={2006 International Electron Devices Meeting},
  year={2006},
  pages={1-4}
}
A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI… CONTINUE READING

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