A 35 ns 64 Mb DRAM using on-chip boosted power supply
@article{Lee1992A3N,
title={A 35 ns 64 Mb DRAM using on-chip boosted power supply},
author={Dong-Jae Lee and Yong-Sik Seok and Do-Chan Choi and Jae-Hyeong Lee and Young-Rae Kim and Hyeun-Su Kim and Dong-Soo Jun and O. H. Kwon},
journal={1992 Symposium on VLSI Circuits Digest of Technical Papers},
year={1992},
pages={64-65}
}An on-chip boosted power supply is necessary for ease of layout and high speed in high density DRAMs. The technique of TTL conversion is a key to designing high speed DRAMs for 3-V operation. The authors present the generation and regulation of an on-chip power supply (V/sub pp/) within 50 mV of the optimum level during operation for a given V/sub cc/. In addition to the regulated V/sub cc/ scheme, improved interface circuit techniques are employed to achieve fast input and output conversion…
5 Citations
Trends in low-power RAM circuit technologies
- EngineeringProceedings of 1994 IEEE Symposium on Low Power Electronics
- 1994
Trends in low-power RAM circuit technologies are reviewed. The following provide major contribution to power reduction: lowering operating voltage by lowering the external supply voltage, half-V/sub…
On-Chip Voltage Generators
- Engineering
- 2001
On-chip voltage generation [5.1–5.8] is becoming increasingly important for memory LSI design, as well as for other LSI designs. This importance is being accelerated by a recent trend toward…
A 3.3 V 16 Mb nonvolatile virtual DRAM using a NAND flash memory technology
- Computer Science1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers
- 1997
The introduced nonvolatile virtual DRAM (NVDRAM) eliminates the need for this redundancy, achieving high performance while reducing power consumption.
A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control
- Computer ScienceJ. Low Power Electron.
- 2009
This paper examines the optimal voltages for minimal power operation for typical data path circuits like adders and multiply-accumulate (MAC) units across various process, voltage, and temperature conditions and under different workloads.
Memory at VLSI Circuits Symposium
- Computer ScienceIEEE Journal of Solid-State Circuits
- 2008
Over the last decades, the Symposium has been the premier forum for memory, putting more emphasis on seminal memory circuits rather than on record-setting performances with actually fabricated full…
References
SHOWING 1-4 OF 4 REFERENCES
A 1-Mbit BiCMOS DRAM using Temperature Compensation Circuit Techniques
- EngineeringESSCIRC '88: Fourteenth European Solid-State Circuits Conference
- 1988
A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap…
An expermental 16Mb DRAM with reduced peak-current noise
- EngineeringSymposium 1989 on VLSI Circuits
- 1989
In high-density DRAM'S, a large peak current of typically 200-300mA occurs when sense amplifiers start latching in a conventional scheme (Figure la), resulting in intolerable power bus noise.…
A 64Mb DRAM With Meshed Power Line And Distributed Sense-amplifier Driver
- Engineering1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1991
A 33ns 64Mb DRAM
- Computer Science1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1991