A 35 ns 64 Mb DRAM using on-chip boosted power supply

@article{Lee1992A3N,
  title={A 35 ns 64 Mb DRAM using on-chip boosted power supply},
  author={Dong-Jae Lee and Yong-Sik Seok and Do-Chan Choi and Jae-Hyeong Lee and Young-Rae Kim and Hyeun-Su Kim and Dong-Soo Jun and O. H. Kwon},
  journal={1992 Symposium on VLSI Circuits Digest of Technical Papers},
  year={1992},
  pages={64-65}
}
An on-chip boosted power supply is necessary for ease of layout and high speed in high density DRAMs. The technique of TTL conversion is a key to designing high speed DRAMs for 3-V operation. The authors present the generation and regulation of an on-chip power supply (V/sub pp/) within 50 mV of the optimum level during operation for a given V/sub cc/. In addition to the regulated V/sub cc/ scheme, improved interface circuit techniques are employed to achieve fast input and output conversion… 
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References

SHOWING 1-4 OF 4 REFERENCES
A 1-Mbit BiCMOS DRAM using Temperature Compensation Circuit Techniques
A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap
An expermental 16Mb DRAM with reduced peak-current noise
In high-density DRAM'S, a large peak current of typically 200-300mA occurs when sense amplifiers start latching in a conventional scheme (Figure la), resulting in intolerable power bus noise.
A 64Mb DRAM With Meshed Power Line And Distributed Sense-amplifier Driver
  • T. Yamada, Y. Nalkata, M. Inoue
  • Engineering
    1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1991
A 33ns 64Mb DRAM
  • Y. Oowaki, K. Tsuchida, H. Hara
  • Computer Science
    1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1991