A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

@article{Cho2007A3B,
  title={A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS},
  author={Lan-chou Cho and Chihun Lee and Shen-Iuan Liu},
  journal={2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={2007},
  pages={48-586}
}
A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the wideband data buffer are discussed. With 2n-1 PRBS input, the measured rms jitter for the recovered data is 1.15ps at 33.72Gb/s. This CDR can tolerate 31 consecutive identical bits with a locking time of 0.2ns (<7b interval). It consumes 73mW from a 1.2V supply excluding the buffers.