A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

@article{Wu2007A3C,
  title={A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM},
  author={Shien-Yang Wu and C. W. Chou and C. Yi. Lin and M. C. Chiang and C. H. Yang and M. Y. Liu and L. C. Hu and C. H. Chang and P. H. Wu and H. F. Chen and S. Y. Chang and S. H. Wang and P. Y. Tong and Y. L. Hsieh and J. J. Liaw and K. H. Pan and C. H. Hsieh and C. Hai-Peng Chen and J. Y. Cheng and C. H. Yao and W. Wan and T. L. Lee and K. T. Huang and K. C. Lin and L. Y. Yeh and K. C. Ku and S. C. Chen and H. J. Lin and S. M. Jang and Y. C. Lu and J. H. Shieh and M. H. Tsai and J. Y. Song and K. S. Chen and V. S. Chang and S. K. Cheng and S. H. Yang and C. H. Diaz and Y. See and M. Liang},
  journal={2007 IEEE International Electron Devices Meeting},
  year={2007},
  pages={263-266}
}
For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS… CONTINUE READING