A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter

Abstract

An adaptive PLL implemented in a 0.9V 32nm process achieves optimal clock data compensation across a wide range of PVT and operating conditions. This is accomplished by an automated supply-noise sensitivity tracking loop which constantly monitors the BER of a tunable critical path circuit. The proposed PLL achieves a 14.5% to 15.6% improvement in processor… (More)
View Slides

Topics

Cite this paper

@article{Kim2013A30, title={A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter}, author={Bongjin Kim and Weichao Xu and Chris H. Kim}, journal={2013 Symposium on VLSI Circuits}, year={2013}, pages={C162-C163} }