A 32b VLSI CPU chip

@article{Beyers1981A3V,
  title={A 32b VLSI CPU chip},
  author={J. W. Beyers and L. Dohse and J. Fucetola and Richard L. Kochis and C. G. Lob and George Taylor and E. R. Zeller},
  journal={1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={1981},
  volume={XXIV},
  pages={104-105}
}
  • J. Beyers, L. Dohse, E. Zeller
  • Published 1981
  • Computer Science
  • 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
This paper will cover a fully-integrated 32b VLSI processing system with six VLSI chips, containing up to 600,000 transistors/chip. Chips are: 32b CPU, I/O processor, memory controller, 128Kb RAM and 528Kb ROM. 

Figures from this paper

A 32b VLSI system
  • J. Beyers, L. Dohse, E. Zeller
  • Computer Science
    1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1982
A fully integrated 32b VLSI processor system, consisting of a set of 6 VLSI chips containing up to 660,000 transistors, fabricated in a 1μ MOS technology, will be described, with emphasis on the
Embedded memory: a key to high performance system VLSIs
  • T. Iizuka
  • Computer Science
    Digest of Technical Papers., 1990 Symposium on VLSI Circuits
  • 1990
TLDR
Current high-performance system VLSIs can afford a large embedded memory on chip, which provides wide memory bandwidth, dedicated memory architecture for application, small chip count and compact system, and better system speed scalability along with Si-technology scaling.
Comparison of MOS processes for VLSI
A comparison of semiconductor technologies for VLSI is presented with particular reference to the limitations imposed by fundamental, technological and circuit-design considerations. Unichannel MOS
An nMOS VLSI process for fabrication of a 32-bit CPU chip
An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency. The technology
Microprocessors—The first twelve years
TLDR
Four generations of microprocessors are considered in detail, along with case studies of popular chip families, and overall industry trends are presented.
Combinatorial digital logic using charge-coupled devices
TLDR
A new approach to circuit design that allows charge-coupled devices to perform combinatorial digital logic in applications requiring large, regular, pipelined architectures such as systolic arrays where the critical performance parameter is throughput per unit power.
An experiment in high level language microprogramming and verification
TLDR
This work provides new results on the efficiency of high level microprogramming languages, the effectiveness of peephole optimization for microcode and the practicality of formal microprogram verification.
Three-dimensional simulation of VLSI MOSFET's: The three-dimensional simulation program WATMOS
TLDR
A computer simulation program based on a three-dimensional model for small-geometry MOSFET's is described, revealing a new insight into VLSI MOSfET devices and can be used to evaluate new VLSi and VHSIC technologies.
VLSI Production with a multi-layer photolithography process
Multi-layer resist processes have been reported by researchers with varying success as applied to a manufacturable photolithography process. Since 1980, Hewlett Packard has used a version of the
Ein 32-Bit-Rechenwerk mit eingebautem Hardware-Selbsttest
TLDR
Das in fehlertolerierenden Mehrprozessorsystemen erforderliche Diagnosesystem baut auf dem Selbsttest der Einzelprozessoren auf, der Fehlererkennungsrate liegt uber 92%, bei den Speicherelementen bei 100%.
...
...