A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS


With the proliferation of the Internet of Things and mobile computing, network speed is accelerating to support data-rich services. This drives the explosion of bandwidth requirement on backplane interconnects while channel length and power efficiency remain intact. This paper presents a 32Gb/s PAM-4 transceiver fabricated in a 65nm CMOS process. It… (More)
DOI: 10.1109/ISSCC.2018.8310210


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