A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS


An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35–1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal… (More)


12 Figures and Tables