A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

@article{Takemura2010A3S,
  title={A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme},
  author={Riichiro Takemura and Takayuki Kawahara and Katsuya Miura and Hiroyuki Yamamoto and Jun Hayakawa and Nozomu Matsuzaki and Kazuo Ono and Michihiko Yamanouchi and Kenchi Ito and Hiromasa Takahashi and Shoji Ikeda and Haruhiro Hasegawa and Hideyuki Matsuoka and Hideo Ohno},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={869-879}
}
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit… CONTINUE READING
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