A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS


This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, an on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An asynchronous clocking scheme realizes… (More)
DOI: 10.1109/JSSC.2012.2217892


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