A 30 MIPS VLSI CPU
@article{Boschma1989A3M,
title={A 30 MIPS VLSI CPU},
author={B. D. Boschma and D. M. Burns and R. Chin and N. S. Fiduccia and C. Hu and M. J. Reed and T. I. Rueth and F. X. Schumacher and V. Shen},
journal={IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers},
year={1989},
pages={82-83}
}A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512…
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