A 30 MHz high-speed analog/digital PLL in 2 mu m CMOS


An analog/digital approach to data clock recovery that allows the implementation of a quasi-digital phase-locked loop (PLL) with an effective local clock frequency of 1 GHz in 2- mu m CMOS is described. The large phase jumps normally associated with digital PLLs are avoided. The basic concept of the clock recovery system is shown. A long ring oscillator (32… (More)


6 Figures and Tables