A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

  title={A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure},
  author={C. Chan and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  journal={2012 Symposium on VLSI Circuits (VLSIC)},
  • C. Chan, Yan Zhu, +2 authors R. Martins
  • Published 2012
  • Computer Science, Engineering
  • 2012 Symposium on VLSI Circuits (VLSIC)
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration. 
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