A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

@article{Chan2012A38,
  title={A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure},
  author={C. Chan and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  journal={2012 Symposium on VLSI Circuits (VLSIC)},
  year={2012},
  pages={86-87}
}
  • C. Chan, Yan Zhu, +2 authors R. Martins
  • Published 2012
  • Computer Science, Engineering
  • 2012 Symposium on VLSI Circuits (VLSIC)
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration. 
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References

SHOWING 1-5 OF 5 REFERENCES
A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS
  • 27
A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture
  • 17
A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS
  • Yung-Hui Chung, J. Wu
  • Computer Science
  • 2011 Symposium on VLSI Circuits - Digest of Technical Papers
  • 2011
  • 23
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS
  • 95
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
  • 53
  • PDF