A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

@article{Chan2012A38,
  title={A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure},
  author={C. Chan and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  journal={2012 Symposium on VLSI Circuits (VLSIC)},
  year={2012},
  pages={86-87}
}
  • C. Chan, Yan Zhu, +2 authors R. Martins
  • Published 2012
  • Computer Science, Engineering
  • 2012 Symposium on VLSI Circuits (VLSIC)
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration. 
View on IEEE
doi.org
53 Citations
Highly Influential Citations
8
Background Citations
26
Methods Citations
10
Results Citations
1

53 Citations

Citation Type

Citation Type

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
  • L. Kull, T. Toifl, +7 authors Y. Leblebici
  • Computer Science
  • 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 2013
  • 58
A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC
  • 2
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
  • 50
  • Highly Influenced
  • PDF
A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer
  • Hai Huang, L. Du, Y. Chiu
  • Materials Science, Computer Science
  • 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)
  • 2015
  • 7
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
  • 205
  • PDF
An 8-bit 900MS/S two-step SAR ADC
  • 3
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique
  • Hyeok-Ki Hong, H. Kang, +5 authors Seung-Tak Ryu
  • Engineering, Computer Science
  • 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
  • 2015
  • 41
  • Highly Influenced
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique
  • 13
A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS
  • 15
  • Highly Influenced
  • PDF
A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS
  • 56
...
1
2
3
4
5
...

References

SHOWING 1-5 OF 5 REFERENCES
A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS
  • 27
A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture
  • 17
A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS
  • Yung-Hui Chung, J. Wu
  • Computer Science
  • 2011 Symposium on VLSI Circuits - Digest of Technical Papers
  • 2011
  • 23
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS
  • 95
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
  • 53
  • PDF