A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology

This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC) operation. Since the DLL has dual DCC circuit, with the combinations of two DCC circuits, the DLL can correct +12.9% and -6.13% duty error under 2% at 333 MHz with 1.6 V. The DLL operates up to 1.67 GHz with 1.8 V and 1.78 GHz with 2.0… CONTINUE READING