A 3.33Gb/s (1200,720) low-density parity check code decoder

@article{Lin2005A3,
  title={A 3.33Gb/s (1200,720) low-density parity check code decoder},
  author={Chien-Ching Lin and Kai-Li Lin and Hsie-Chia Chang and Chen-Yi Lee},
  journal={Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.},
  year={2005},
  pages={211-214}
}
In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved… CONTINUE READING
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