A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

@article{Oh2015A3G,
  title={A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation},
  author={Tae-Young Oh and Hoeju Chung and Jun-Young Park and Ki-Won Lee and Seung-Hoon Oh and Su-Yeon Doo and Hyoung-Joo Kim and ChangYong Lee and Hye Ran Kim and Jong-Ho Lee and Jin-Il Lee and Kyung-Soo Ha and Young-Ryeol Choi and Young-Chul Cho and Yong-Cheol Bae and Taeseong Jang and Chulsung Park and Kwang-Il Park and Seong-Jin Jang and Joo-Sun Choi},
  journal={IEEE Journal of Solid-State Circuits},
  year={2015},
  volume={50},
  pages={178-190}
}
A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with… CONTINUE READING