A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

@article{Kull2013A38,
  title={A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS},
  author={Lukas Kull and Thomas Toifl and Martin L. Schmatz and Pier Andrea Francese and Christian Menolfi and Matthias Braendli and Marcel A. Kossel and Thomas Morf and Toke Meyer Andersen and Yusuf Leblebici},
  journal={2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers},
  year={2013},
  pages={468-469}
}
Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking, redundant capacitive DACs (CDAC), multi-bit decisions per step and interleaved designs have been presented. We present an asynchronous redundant single-channel ADC achieving 1.2GS/s at 1V supply by using two comparators in alternation to relax comparator reset timing. The ADC achieves 39… CONTINUE READING
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