A 3-GHz dual-modulus prescaler based on improved master-slave DFF

Abstract

An integrated low-power 3-GHz dual-modulus prescaler (DMP) divided-by-32/33 with a great tolerance to the clock-edge is presented in this paper. A novel structure of CMOS MS-DFF (master-slave D flip-flop) is used in the asynchronous part of the prescaler. The DFF based on the structure can work well in the clocks with longer clock-edge and overcome general… (More)

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