A 3/5 V compatible I/O buffer

@inproceedings{Pelgrom1995A3V,
  title={A 3/5 V compatible I/O buffer},
  author={Marcellinus Johannes M Pelgrom and Eke Carel Dijkmans},
  year={1995}
}
The design of a digital input/output buffer is described for operation in 3.3-V IC's with 5-V input signals. The design has been processed in 0.8- and 0.6-/spl mu/m CMOS processes. A comparison of results is presented. > 

Topics from this paper.

Citations

Publications citing this paper.
SHOWING 1-10 OF 63 CITATIONS

Design on new tracking circuit of I/O buffer in 0.13-/spl mu/m cell library for mixed-voltage application

  • 2006 IEEE International Symposium on Circuits and Systems
  • 2006
VIEW 3 EXCERPTS
CITES METHODS
HIGHLY INFLUENCED

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2006
VIEW 8 EXCERPTS
CITES BACKGROUND
HIGHLY INFLUENCED

Reliable , High-Performance I / O Buffer Design for Multiple Power Supply Systems

VIEW 4 EXCERPTS
CITES BACKGROUND, METHODS & RESULTS
HIGHLY INFLUENCED

Design of Power Management Unit Using Mixed Voltage Buffer

  • 2017 IEEE 7th International Advance Computing Conference (IACC)
  • 2017

A 1.8/2.5/3.3V BiCMOS I/O driver with VCC=5V

  • 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
  • 2014

FILTER CITATIONS BY YEAR

1997
2017

CITATION STATISTICS

  • 4 Highly Influenced Citations