A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor

@article{Chun2012A2E,
  title={A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor},
  author={Ki Chul Chun and Wei Zhang and Pulkit Jain and Chris H. Kim},
  journal={IEEE Journal of Solid-State Circuits},
  year={2012},
  volume={47},
  pages={2517-2526}
}
A truly logic-compatible gain cell eDRAM macro with no boosted supplies is presented. A 2T1C gain cell implemented only with regular thin oxide devices consists of an asymmetric 2T cell and a coupling PMOS capacitor. The PMOS capacitor ensures proper operation even without a boosted supply by utilizing a beneficial coupling for read and a preferential boosting for write. A repair scheme based on a single-ended 7T SRAM has features such as a local differential write and shared control with the… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-10 OF 19 CITATIONS

Estimating the Energy Consumption of Emerging Random Access Memory Technologies

VIEW 5 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2017
VIEW 5 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2014
VIEW 4 EXCERPTS
CITES RESULTS & BACKGROUND
HIGHLY INFLUENCED

Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits

  • 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)
  • 2019
VIEW 1 EXCERPT
CITES METHODS

Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory

  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • 2016
VIEW 1 EXCERPT
CITES BACKGROUND

References

Publications referenced by this paper.
SHOWING 1-10 OF 14 REFERENCES

A 45 nm 8-Core Enterprise Xeon¯ Processor

  • IEEE Journal of Solid-State Circuits
  • 2009
VIEW 3 EXCERPTS
HIGHLY INFLUENTIAL

A 45 nm SOI embedded DRAM macro for the POWERTMprocessor 32MByte on-chip L3 cache

J. Barth
  • IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 64–75, Jan. 2011.
  • 2011
VIEW 1 EXCERPT

A 500 MHz random-access embedded 1 Mb DRAM macro in bulk CMOS

S. Romanovsky
  • IEEE ISSCC Dig. Tech. Papers, 2008, pp. 270–271.
  • 2008
VIEW 1 EXCERPT