A 2GHz 16dBm IIP3 low noise amplifier in 0.25/spl mu/m CMOS technology

@article{Youn2003A21,
  title={A 2GHz 16dBm IIP3 low noise amplifier in 0.25/spl mu/m CMOS technology},
  author={Yong-Sik Youn and Jae-Hong Chang and Kwang-Jin Koh and Young-Jae Lee and Hyun-Kyu Yu},
  journal={2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
  year={2003},
  pages={452-507 vol.1}
}
A 2GHz LNA implemented in a 0.25/spl mu/m CMOS technology delivers 14dB gain, 2.8dB NF and 16dBm IIP3. High linearity is obtained by a third-harmonic cancellation technique using a stacked triode structure with differential signals. The method, based on DC non-linear characteristics, improves delay equalization from DC-2GHz with a 17% power increase, 0.8dB gain reduction, and <0.1dB NF increase. 
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