A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure

  title={A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure},
  author={Tadato and Yamagata and Masaaki and Mihara and Takeshi and Hamamoto and Yasumitsu and Murai and Toshifumi and H Kobayashi and Michihiro and Yamada and Hideyuki and Ozaki},
AZNract-Thk paper describes a 288-kb (8K words X 36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 pmz) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is… CONTINUE READING
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A high-speed string-search engine,

  • H. Yamada, M. Hirata, H. Nagai, K. Takahashi
  • IEEE J. Solid-State Circuits, vol
  • 1987

Low - cost associative memory Dynamic cross - coupied bitline content addressable memory cell for high density arrays

  • N. Hashimoto
  • 1980

A 1 Kbit associative memory LSI,

  • T. Nikaido, T. Ogura, S. Hamagrrchi, S. Muramoto
  • Japan. J. Appl. Phys.,
  • 1966

A high - speed CAM based architecture for a prolog machine ( ASCA )

  • H. A. Schneider, S. Yamada, T. Kimura
  • IEEE Trans . Comput .

Content - addressable memory for VLSI pattern inspection

  • J. T. Walker S. I. Chae, C.-C. Fu, R. F. Pease
  • IEEE J . Solid - State Circuits

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