A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure

@inproceedings{Tadato1992A2F,
  title={A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure},
  author={Tadato and Yamagata and Masaaki and Mihara and Takeshi and Hamamoto and Yasumitsu and Murai and Toshifumi and H Kobayashi and Michihiro and Yamada and Hideyuki and Ozaki},
  year={1992}
}
AZNract-Thk paper describes a 288-kb (8K words X 36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 pmz) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is… CONTINUE READING
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