A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS

@article{Sun2014A2F,
  title={A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS},
  author={Li Sun and Quan Pan and Keh-Chung Wang and C. Patrick Yue},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2014},
  volume={61},
  pages={2139-2149}
}
This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm2. Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty… CONTINUE READING

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