A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS

@article{Iwata2009A2M,
  title={A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS},
  author={Kenichi Iwata and Seiji Mochizuki and Michitaka Kimura and Tetsuya Shibayama and Fumitaka Izuhara and Hiroaki Ueda and Koji Hosogi and Hiroaki Nakata and Masakazu Ehama and T. Kengaku and Taiki Nakazawa and Hiromi Watanabe},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={1184-1191}
}
A video-size-scalable H.264 high-profile codec including 19 application-specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the codec consumed 256 mW in real-time encoding of 40 Mbp full-HDs (1080p30) video at an operating frequency of 162 MHz. 

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