A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

@article{Calhoun2007A26,
  title={A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation},
  author={B. H. Calhoun and A. P. Chandrakasan},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={680-688}
}
Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the… CONTINUE READING
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A SRAM design on 65 nm CMOS technology with integrated leakage scheme

  • K. Zhang, U. Bhattacharya, +6 authors M. Bohr
  • Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp…
  • 2004
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