A 25/50MHz dual-mode parallel multiplier/accumulator

Abstract

A 12 × 12 parallel multiplier/accumulator using standard 3μm bipolar oxide-isolated ISL technology will be described. A gated pipeline-register which can be bypassed allows the chip to be used in a direct mode at a 25MHz rate or in a pipeline mode at a 50MHz clock rate. Power dissipation is 900mW. 

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Cite this paper

@article{Welten1984A2D, title={A 25/50MHz dual-mode parallel multiplier/accumulator}, author={F. Welten and J. Lohstroh and A. Linssen}, journal={1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers}, year={1984}, volume={XXVII}, pages={86-87} }