A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

  title={A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications},
  author={M. Tikekar and Chao-Tsung Huang and C. Juvekar and V. Sze and A. Chandrakasan},
  journal={IEEE Journal of Solid-State Circuits},
  • M. Tikekar, Chao-Tsung Huang, +2 authors A. Chandrakasan
  • Published 2014
  • Computer Science
  • IEEE Journal of Solid-State Circuits
  • High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage… CONTINUE READING
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