A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

@article{Tikekar2014A2H,
  title={A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications},
  author={Mehul Tikekar and Chao-Tsung Huang and Chiraag Juvekar and Vivienne Sze and Anantha Chandrakasan},
  journal={IEEE Journal of Solid-State Circuits},
  year={2014},
  volume={49},
  pages={61-72}
}
High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage… Expand
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