A 237 Gbps Unrolled Hardware Polar Decoder


In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput of over 237 Gbps for a (1024,512) polar code implemented using an FPGA. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.

DOI: 10.1049/el.2014.4432

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@article{Giard2014A2G, title={A 237 Gbps Unrolled Hardware Polar Decoder}, author={Pascal Giard and Gabi Sarkis and Claude Thibeault and Warren J. Gross}, journal={CoRR}, year={2014}, volume={abs/1412.6043} }