A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

@article{Jan2012A2S,
  title={A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications},
  author={C.-H. Jan and Uddalak Bhattacharya and Ruth A. Brain and Sungchan Choi and Gregorio Curello and Gaytri Gupta and Walid Mahmoud Hafez and Myungsu Jang and Min-Soo Kang and K. Komeyli and T Kenny Leo and N. Nidhi and Li Li Pan and Joodong Park and K. Phoa and Anisur Rahman and Chad Staus and Hiroyuki Tashiro and C. Tsai and P. Vandervoorn and Li Yang and J.-Y. Yeh and P. Bai},
  journal={2012 International Electron Devices Meeting},
  year={2012},
  pages={3.1.1-3.1.4}
}
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um… CONTINUE READING

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( NO TITLE )

  • E Karl
  • 2012

Tech

  • C Auth
  • Tech
  • 2012

Dig

  • C.-H Jan
  • Dig
  • 2009

( NO TITLE )

  • K Mistry
  • 2007

Dig

  • T Ghani
  • Dig
  • 2003

( NO TITLE )

  • D Ingerly

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