A 210-GHz Amplifier in 40-nm Digital CMOS Technology

Abstract

This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

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Cite this paper

@article{Ko2013A2A, title={A 210-GHz Amplifier in 40-nm Digital CMOS Technology}, author={Chun-Lin Ko and Chun-Hsing Li and Chien-Nan Kuo and Ming-Ching Kuo and Da-Chiang Chang}, journal={IEEE Transactions on Microwave Theory and Techniques}, year={2013}, volume={61}, pages={2438-2446} }