A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

@article{Kim2012A2N,
  title={A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface},
  author={Chulbum Kim and Jinho Ryu and Tae-Sung Lee and Hyunggon Kim and Jaewoo Lim and Jaeyong Jeong and Seonghwan Seo and Hongsoo Jeon and Bokeun Kim and Inyoul Lee and Dooseop Lee and Pansuk Kwak and Seongsoon Cho and Yongsik Yim and Changhyun Cho and Woopyo Jeong and Kwang-Il Park and Jin-Man Han and Duheon Song and Kyehyun Kyung and Youngho Lim and Young-Hyun Jun},
  journal={IEEE Journal of Solid-State Circuits},
  year={2012},
  volume={47},
  pages={981-989}
}
A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed. 
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