A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

@article{Chang2013A21,
  title={A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications},
  author={Jonathan Chang and Yen-Huei Chen and Hank Cheng and Wei-Min Chan and Hung-Jen Liao and Quincy Li and Stanley Chang and Sreedhar Natarajan and Robin Lee and Ping-Wei Wang and Shyue-Shyh Lin and Chung-Cheng Wu and Kuan-Lun Cheng and Min Cao and George H. Chang},
  journal={2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers},
  year={2013},
  pages={316-317}
}
A 20nm high-κ metal-gate planar CMOS technology is optimized and developed for SoC platform applications that span a wide range of power and performance. This technology is based on a 20nm SoC process featuring high-κ metal gate and strain techniques for core logic transistors with low-power/high-performance and I/O transistors. A high-density and a high-performance embedded memory bit cell each has an area <;0.1μm2. This technology is targeted to high-density low-cost low-power high… CONTINUE READING
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