A 20MHz bandwidth continuous-time ΣΔ modulator with jitter immunity improved full-clock period SCR (FSCR) DAC and high speed DWA

Abstract

A 20MHz bandwidth continuous-time ΣΔ modulator with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) DAC for feedback. A new data weighted averaging (DWA) technique is adopted to remove the timing… (More)

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