A 204.8GHz Static Divide-by-8 Frequency Divider in 250nm InP HBT

@article{Griffith2010A2S,
  title={A 204.8GHz Static Divide-by-8 Frequency Divider in 250nm InP HBT},
  author={Zach Griffith and Miguel Urteaga and Richard Pierson and Petra Rowell and Mark J. W. Rodwell and B. Brar},
  journal={2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)},
  year={2010},
  pages={1-4}
}
We present a static divide-by-8 frequency divider with a record maximum clock frequency of 204.8GHz, designed and fabricated using 250nm InP HBTs (400GHz ft, 650GHz fmax) with a 4-metal layer, inverted thin-film microstrip wiring environment. The divider is fully static down to 4.0GHz operation. The total power dissipation is 1.82W, of which 592mW is consumed by the input-stage divider. The divider latches are formed using emitter-coupled-logic (ECL), and inductive peaking is used in series… CONTINUE READING