A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

@article{Sanchez1996A2M,
  title={A 200 MHz 2.5 V 4 W superscalar RISC microprocessor},
  author={Hector Sanchez and Lee Eisen and Cody Croxton and Arthur R. Piejko and Carmine Nicoletta and Ivan Vo and Bernard M. Branson and Wen Wang and Quan Nguyen and Taqi N. Buti and L.-C. Hsu and M. J. Saccamango and S. Ratanaphanyara and Ross Philip and Jq. Alvarez and Steve Weitzel and Gianfranco Gerosa},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  year={1996},
  pages={218-219}
}
This RISC microprocessor is based on a microarchitecture designed in a 2.5 V CMOS technology. The 78.75 mm/sup 2/ design features dual 16 kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a load/store unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2/spl times/, 2.5/spl times/, 3/spl times/, 3.5/spl times/, 4/spl times/, 4.5/spl times/, 5/spl… CONTINUE READING