A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS

Abstract

The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It… (More)
DOI: 10.1109/JSSC.2010.2049458

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8 Figures and Tables