A 20 ns, low power, NMOS 1Kx4 static RAM


Using scaled NMOS processing and novel circuit design techniques to enhance the speed-power product, a high-speed, low power, fully static 1024-word/spl times/4-bit random access memory has been developed. Applications related requirements such as fast chip select access time and /spl times/4 organization for cache and microcode store memories are central… (More)


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@article{Rhodes1981A2N, title={A 20 ns, low power, NMOS 1Kx4 static RAM}, author={C. Rhodes and R. Pinkham and F{\'a}tima Valente and R. Douglas Ramsey}, journal={IEEE Journal of Solid-State Circuits}, year={1981}, volume={16}, pages={594-597} }