A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

@article{Kim2005A2P,
  title={A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS},
  author={Jaeha Kim and Jeong-Kyoum Kim and Bong-Joon Lee and Namhoon Kim and Deog-Kyoon Jeong and Wonchan Kim},
  journal={Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.},
  year={2005},
  pages={144-147}
}
A 20GHz phase-locked loop with 4.9ps/sub pp//0.65ps/sub rms/ jitter and -101.2dBc/Hz phase noise at 1MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled-microstrip resonator. Static frequency dividers made of pulsed latches operate faster than a… CONTINUE READING
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