A 2.9ns random access cycle embedded DRAM with a destructive-read

@article{Hwang2002A2R,
  title={A 2.9ns random access cycle embedded DRAM with a destructive-read},
  author={Chomg-Lii Hwang and Toshiaki Kirihata and M. Wordernan and John Fifield and D. Storaska and D. Pontius and G. Fredernan and B. Ji and Steven W. Tomashot and Sang H. Dhong},
  journal={2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)},
  year={2002},
  pages={174-175}
}
High performance devices available in a logic-based embedded DRAM process can be used to significantly improve eDRAM performance. However, random access cycle time of conventional eDRAMs remains around 6 ns. In this work, a novel destructive-read architecture that reduces the random access cycle time of an eDRAM by delaying the data write back operation to a later cycle is demonstrated. A single-ended direct sensing is employed to further speed up the random access cycle time of the eDRAM to 2… CONTINUE READING
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